Packet latency may be affected by processor utilization. On a per packet basis, one of the main contributors to processor utilization includes interrupt processing. For example, when a packet arrives at a network controller, the network controller may interrupt the system to indicate that a packet is available for processing. On a typical system, for example, processing an interrupt may consume approximately 8000 processor cycles. Hypothetically, if a network controller interrupts the system for every packet it receives, then a 10 Gigabit Ethernet network controller would interrupt the system approximately 8560001 times a second.
To achieve high efficiency (i.e., low processor utilization), therefore, the number of interrupts may be reduced. A common technique for reducing interrupts is using interrupt coalescing. Interrupt coalescing refers to a scheme in which the network controller waits for a condition to be met before interrupting the system, where the condition may be the arrival of a certain number of packets or the passing of a fixed amount of time. While increasing efficiency is desirable for certain applications (e.g., bulk data transfers), current schemes for achieving high efficiency, such as interrupt coalescing, may also increase packet latency, which may be unacceptable for certain applications (e.g., latency sensitive applications such as remote procedure calls, file system protocols, and RTSP (real time streaming protocol), RFC 2326 published April 1998, available from IETF (Internet Engineering Task Force), for example). For example, if a particular interrupt coalescing scheme generates an interrupt after every nth packet is received, then the nth+1 packet would remain in the network controller buffers until generation of the next interrupt.